1. Field of the Invention
The present invention relates to a method of fabricating a bipolar junction transistor (BJT), and more particularly, to a method of fabricating a vertical BJT.
2. Description of the Prior Art
A BJT utilizes two types of carriers, “electrons” and “hot holes”, to transmit current. The BJT continues to be a basic circuit element in integrated circuits due to its high switching capability and current carrying capacity. A BiCMOS transistor is constructed by a particular combination of the BJT and a complementary metal oxide semiconductor (CMOS) transistor positioned on the same integrated circuit, so as to speed up an operation of the CMOS transistor. Currently, multiple masking steps are used to combine sequences of the BJT fabrication steps and the CMOS transistor fabrication steps, which increasing complication of the total processing steps.
Referring to FIGS. 1-6, FIGS. 1-6 are schematic diagrams of a method of fabricating a BJT according to the prior art. In the conventional method of fabricating a BiCMOS transistor, masking steps for fabricating the BJT are added into the processing steps of the CMOS transistor. Since the processing steps of the CMOS transistor are already well known by the current industry, they are not shown in FIGS. 1-6. FIGS. 1-6 are focused on illustrating the processing steps of the BJT only. As shown in FIG. 1, a P− silicon substrate 10 having a buried N+ doping region 12 and an N+ epitaxial layer 14 positioned on the buried N+ doping region 12 is provided. Normally, the buried N+ doping region 12 is positioned at a predetermined depth within the substrate 10. In order to avoid a misalignment between the buried N+ doping region 12 and other devices, several alignment marks (not shown) are often formed on the substrate 10, for example formed in scribe lines of the substrate 10.
As shown in FIG. 2, an N well 16 is formed on the substrate 10, and a plurality of field oxide layers 20 are formed on the N well 16 to define positions for forming a collector and a base of the BJT. Following that, an ion implantation process is performed to form a buried P+ doping region 18 around the N well 16. The buried P+ doping region 18 is used as a channel stop to prevent ions of the N well 16 from diffusing into adjacent devices.
As shown in FIG. 3, another ion implantation process is performed to form an N+ collector 22 in the N well 16. A thermal treatment is then used to drive in the N well 16 and the N+ epitaxial layer 14 into the N+ collector 22, thus contacting the N+ collector 22 with the buried N+ doping region 12. As shown in FIG. 4, a mask 24 is formed in the substrate 10, the mask 24 having an opening therein to expose the position for forming the base of the BJT. Following that, an ion implantation process is performed to form a P+ base 26 on a portion of the N well 16 not covered by the mask 24.
As shown in FIG. 5, a doped polysilicon layer 28 is deposited on the substrate 10 followed by using a photolithographic process and an etching process to remove a portion of the polysilicon layer 28, thus forming an N+ emitter 28 on the P+ base 26. Normally, the deposition process of the polysilicon layer 28 can be used to deposit a polysilicon layer of a gate structure of the CMOS transistor, too. In addition, the polysilicon layer 28 can be doped together with a source/drain of the CMOS transistor. Following that, depending on the characteristic demands of the products, a spacer 30 is optionally formed on either side of the N+ emitter 28, so that a self-aligned silicidation process can be used to form a silicide layer on surfaces of the N+ collector 22, the P+ base 26 and the N+ emitter 28 to reduce their contact resistance. Alternatively, a dielectric layer (not shown), such as a borophosphosilicate glass (BPSG) can be formed on the substrate 10. The dielectric layer has several openings therein to respectively connect to the N+ collector 22, the P+ base 26 and the N+ emitter 28, thus enabling a subsequent process to form several self-aligned contact plugs to connect to the N+ collector 22, the P+ base 26 and the N+ emitter 28, respectively.
As mentioned above, a plurality of masks are used to fabricate the BJT according to the prior art. For example, different masks are required to define the patterns of the alignment marks, the buried N+ doping region 12, the buried P+ doping region 18, the N+ collector 22, the P+ base 26 and the N+ emitter 28, and to combine the sequences of the BJT fabrication steps with the CMOS transistor fabrication steps. In this case, the total processing steps of the BJT become very complicated. In addition, during the repeated masking steps, such as forming the masks and removing the masks, the device is possible damaged to have a bad electrical performance.